The present disclosure herein relates to methods of manufacturing three-dimensional semiconductor devices and related three-dimensional semiconductor devices.
Recently, demand for higher integration of semiconductor devices has increased to obtain improved performance and/or low price for user needs. In semiconductor memory devices, higher integration may be particularly required, since integration is a significant factor in determining prices. In two-dimensional or planar semiconductor devices, since the integration degree mainly depends on an area occupied by a unit memory cell, integration is affected by the technique(s) used to form fine patterns. In order to realize minute patterns, however, an increase in integration of the two dimensional semiconductor devices may be restricted since it may be necessary to install expensive equipment.
In order to overcome these restrictions, there have been suggested three-dimensional semiconductor devices including memory cells arranged three-dimensionally. In order to realize mass production of the three-dimensional devices, however, a manufacturing technique may be required to achieve reliable product characteristics while reducing a manufacturing cost per bit more than that of two dimensional semiconductor devices.